Small Hardware Description Language

SHDL | Decoder | CompMux | Register

3 Register

3.1 Flip-flop

Sequential circuits in SHDL are constrained to synchronous circuits with a single clock signal named clk. The sequential SHDL circuits change state at the rising edge of the clock; this is in VHDL equivalent to condition if rising_edge(clk).

Circuits are described with synchronous assignment operator <= used to notify, that the assignment will execute only after the rising edge of the clock. A basic D flip-flop is only one line in SHDL:

q <= d

Assuming d and q are one bit signals, this line translates in generated VHDL to a process with the clock condition and optional asycnhronous reset (depending on SHDL Setup):

-- VHDL: no async reset 

process(clk)
begin
 if rising_edge(clk) then
  q <= d;
 end if;
end process;

   
process(clk, rst)
begin
 if rst='1' then
  q <= '0';
 elsif rising_edge(clk) then
  q <= d;
 end if;
end process;

With additional conditions one can model a flip-flop including synchronous control inputs. An example of D flip-flop with set and clock enable: dff

if enable then
  if set then
    q <= 1
  else
    q <= d
  end
end

3.2 Register

Registers are storing vector values and have load control signal for changing the values. Description of a register is similar to D flp-flop with enable, only the data input and output are declared as multi-bit vectors: reg

entity reg
load: u1;
r, data: u8;
begin
 if load then
   r <= data
 end
end

3.3 Shift register with flip-flops

Shift registers are used for parallel serial data transformations. We will look at SIPO and PISO shift register models. They are composed of D flip-flops and multiplexers.

3.3.1 SIPO with flip-flops

A Serial-In-Parallel-Out (SIPO) register is made form connected D flip-flops. The first flip-flops receives data from serial input and sends ouput to the next flip-flop. The flip-flops are described with multiple assignment statements, for example a 4-bit SIPO: sipo

q0<=d
q1<=q0
q2<=q1
q3<=q2

output=q3 & q2 & q1 & q0

The 4-bit vector output is assigned a composed value of all the internal flip-flops. Note that the combinational assignment operator is used for the output, because the composition should be made of wires and not additional flip-flops.

3.3.2 PISO with flip-flops

A Parallel-In-Serial-Out (PISO) register loads parallel data and shifts the data to the serial output. A small 4-bit PISO model with explicit flip-flops: piso1

if load then
  q0<=d(0); q1<=d(1); q2<=d(2); q3<=d(3);
else
  q0<=q1; q1<=q2; q2<=q3; q3<=0;
end
o=q0

The shift register has four one-bit signals q0...q3 and 4-bit input d. When load is 1, the flip-flops q0...q3 store input data and when the load is 0, the data is shifted. The value of q0 is replaced with q1, q1 with q2, q2 with q3 and the most significant bit is set to 0. Finally, there is a combinational assignment to send the least significant bit to the oputput o.

3.3.3 PISO with shift operator

A more concise PISO model is described with shift operators. The operator srl shifts a vector value to the right for a specified number of bits: piso2

if load then
  q<=d
else
  q<=q srl 1
end
o=q(0)

3.3.4 Shift register with parallel and serial input

The PISO can have additional serial input for the value shifted to the flip-flops (instead of zero). The shift expression can be described with subvector selection and composition: piso3

if load then
  q<=d
else
  q<=ser & q(3 downto 1)
end
o=q(0)

Exercises