Default data type: bits
Language:
VHDL (and, or, xor, not, &, =, /=)
VHDL-2008
Verilog (&, |, ^, ~, <<, >>, ==, !=)
std_logic ports async reset RTL
Error report: mark english
Sim period: ns save waveform Board
(c) A. Trost, Fakulteta za elektrotehniko, LNIV, 2018-2022