This is a brief presentation of online digital circuit design educational tool with SHDL, a hardware description language based on simplified VHDL syntax. The tool is used to design small digital circuit models in a web browser, simulate the models with a graphical test bench and automatically convert to synthesizable VHDL.
|1. New Model||2. Model Parsing||3. Simulation|
A digital circuit model is described in simplified language SHDL. The model consists of entity name, signal declarations and statement block between begin in end. An example of 4-bit counter with count enable (en):
The statement block contains signal assignment and conditional statements in simplified VHDL syntax. Statements present parts of a digital circuit operating in parallel (e.g. concurrent data-flow operations). The SHDL modeling rules:
=describes combinational logic. A set of VHDL-like operators is used for describing assigned expressions:
<=describes sequential logic, where the assignment is executed on rising edge of the clock. There is only one clock signal in the model, which is automatically inferred when using sequential assignments (you should not define clk in circuit ports).
A click to Parse starts model analysis, parsing and transformation. The parser messages appear below the code editor. Successful parsing produces a message "Parse finished.", otherwise the error description appears.
Example: the code line cnt >= cnt + 1 outputs error:
Parse Error at 6:12: Expecting '='!
with information about error location (line 6, character 12) and description that the compiler expects assignment operator.
The circuit model is transformed into internal descriprion presented in Analysis tab. Summary of the parsed circuit model resource estimation is available there. The model transformed to VHDL can be found in the VHDL tab. A click to copy is used to select and copy the generated code to clipboard for an easy transfer to external VHDL-based tools.
Parsing the model updates the simulation waveform with the signals from the model table. To prepare simulation, you have to enter the number of clock cycles and set the input signals. By clicking on the waveform of an one-bit input signal, the signal value toggles between zero and one. Multi-bit input signals are set to a given integer value by entering value into the form and clicking on the waveform.
The simulation is executed with a click on Run and we can immediately observe the resulting waveform. If you click Run next time, the simulation executes again, but this time starting from the last state of the circuit (this is important for sequential circuits). In order to start simulation from the reset state, you have to parse the model again and then click on Run.
The SHDL tool preforms analysis of the described circuit model. Reports accesible at the tab Analysis include: parsed model code (Visit), estimated circuit area (Resources) and circuit data-flow graph (DFG). Resource summary presents the number of input-output pins, flip-flops, logic, arithmetic and comparisson operators, and multiplexers.
The circuit area is estimated by decomposing the circuit into a data-flow graph and evaluating graph nodes as circuit building blocks. The reported building blocks (eg. mux, cmp, add) area is based on evaluation of syntesized circuits in CMOS technology. The esimated ASIC circuit area is sum of building blocks areas normalized to the size of a standard 2-input NAND2 gate and divided into combinational and sequential (flip-flop) circuit parts. The expected sinthesized circuit area is usually smaller, due to the optimization, but the SHDL estimation is still useful as a guide to compare various circuit models.
Example: Analysis of an 8-bit modulo counter.
The counter circuit consists of an 8-bit multiplexer (mux8), a comparator (cmp8) and an adder (add8). Total estimated combinatinal logic area is 47 standard NAND2 gates and sequential area is 42 NAND2 gates.
The SHDL tool is regularly updated with additional features, for example interactive virtual board support.