SHDL | Decoder | CompMux | Register
Binary comparators are composed of logic gates xor. A comparator can be described with a Boolean equation. For example a 4-bit non-equality comparator has an output dif which is set, when the inputs are different:
dif = (a(3) xor b(3)) or (a(2) xor b(2)) or (a(1) xor b(1)) or (a(0) xor b(0))
The high-level descritopn of a comparator is based on relational operators (=, /=, <, <=, >, >=) which leads to much more descriptive code. The relational operatos are used in conditions, so the comparator is described with a cinditional statement: comp1
if (a/=b) then
dif = 1
else
dif = 0
end
A shorter HDL description is with conditional assignment operator: comp2
dif = 1 when a/=b else 0;
Describing coparators with operator produces short and easy-to-understand circuit model. The logic circuit for comparing the vectors is produced by the synthesis tools which builds the gate lavel circuit model and takes care of the implementation details (for example difference between signed and unsigned magnitude comparisson circuits).
A multipexer can be described by a sequence of if statements comparing the control input to
constant values.
An example of 4-1 multipexer with inputs d0,d1,d2,d3, 2-bit control signal s and output o:
mux1
if s=0 then o = d0
elsif s=1 then o = d1
elsif s=2 then o = d2
else o = d3
end
A multiplexer can have additional input enable. When it is 0, the output is allways 0, when the enable is 1, the multipexer operates normally. The multiplexer with enable can be described with different models. Note: the enable signal is one-bit and you can shorten the condition in SHDL; instead of if en=1 then, you can write: if en then:
| nested condition (2.3.1) | condition sequence (2.3.2) | default output (2.3.3) |
|---|---|---|
if en then
|
if s=0 then o = d0
|
o = 0
|
A multipexer in general has vector data inputs and output. If the multiplexer has one-bit data,
one can combine all the inputs in one vector and write an expression selecting appropriate bit.
An example of an 8-1 multiplexer: mux2
entity mux2
d: in u8;
s: in u3;
o: out u1;
begin
o = d(s)
end