SVlog syntax reference

2Types and declarations

logic [7:0] a, b;           // unsigned vector
logic signed [7:0] s;       // signed vector
wire [3:0] w;
int i;                       // signed 32 bits (also integer)
logic [3:0][7:0] pk;        // packed array: 4 bytes = 32 bits
logic [7:0] mem [0:255];    // unpacked array (memory)
logic [7:0] regs [8];       // same as [0:7]

Values are 2-state: '0 and '1 fill to the context width; x / z literals are not supported.

3Literals

4Continuous assignment

assign y = a | b;
assign x[3:0] = y[7:4];
assign {cout, sum} = a + b;   // concatenation target

Concatenation operands are self-determined; unsized constants inside {} are errors. assign targets need constant indexes.

5Combinational: always_comb

always_comb begin
  y = a;                    // default avoids latches
  if (sel == 2'd1)      y = b;
  else if (sel == 2'd2) y = a + b;
end

• Blocking = only
• Shorthands: x++ x-- += -= *= &= |= ^= <<= >>=
• A block is not sensitive to signals it writes itself, so sum = sum + a[i] works

A signal that is not assigned on every path (an if without else, a case without default that does not cover every value) gives a latch warning. So do bits left unassigned, as in y[0] = a; for a 4-bit y. Reading a signal before the block assigns it (y = y + a;, a temporary used before it is set) gives a read before assignment warning.

Each bit should be assigned in one block only (assign, always_comb or always_ff): the same bits written in two blocks give a multiple driver warning.

6Sequential: always_ff

always_ff @(posedge clk or negedge rst_n)
  if (!rst_n) q <= '0;
  else        q <= d;

• Non-blocking <= only
• Single clock: the first event (posedge); further events (or / ,) are asynchronous resets
• Each cycle: clock edge, inputs change, logic settles, values sampled

7case statements

[unique|priority] case (sel)    // also casez, casex
  2'd0, 2'd1: y = a;
  2'd2:       y = b;
  default:    y = '0;
endcase

• First matching item wins
• In casez the digits ? / z are don't care (4'b1???); casex adds x
• unique / priority are accepted but not checked

8Enumerations (FSM states)

typedef enum logic [1:0] {IDLE, RUN, DONE = 2'd3} state_t;
state_t state, next;
enum logic {OFF, ON} mode;    // anonymous

• Base type logic/bit [..] or int (default)
• The waveform shows enum signals by member name

9Parameters

module m #(parameter W = 8, localparam M = W*2) (...);
parameter N = 4;
localparam [7:0] K = 8'hA5;
localparam int D = N * 2;

• Usable in ranges, selects, replication, enum values, case items and loops
• No overrides: parameters keep their defaults

10for loops

always_comb begin
  cnt = '0;
  for (int i = 0; i < 8; i++)
    cnt += a[i];
end

• In always_comb and always_ff
• Step: i++ i-- ++i --i i += e i -= e i = e; at most 65 536 iterations
• Loop variables do not appear in the waveform

11Arrays

w[2]  w[2][3:0]  w[2:1]       // packed: one select per dim
mem[addr] <= din;             // variable index ok
logic [7:0] rom [0:3] = '{8'h11, 8'h22, 8'h33, 8'h44};
logic [15:0] t [0:9] = '{2: 200, 5: 500, default: 0};
logic [1:0] r [16] = '{2'b01, 2'b10, default: 2'b00};

• Out-of-range variable index: reads 0, writes ignored
• Part-select bounds must be constant
• No array ports, slices mem[a:b] or second unpacked dimension

12Signed arithmetic

• An expression is signed only if all operands are signed
• Signed expressions sign-extend; part-selects and comparison results are unsigned
• Use $signed(x) / $unsigned(x) to convert
• The waveform shows signed signals as signed decimals

13Stimulus block

/* stimulus 32
   rst   1 0
   en    1*12 0*3 1
   d     0x9 0b0101 -3
*/

stimulus <cycles>, then one line per input: values with optional *count repeats; the last value lasts to the end. Decimal, 0x hex, 0b binary, negative decimals.