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Default data type: bits

Operators:
VHDL (and, or, xor, not, &, =, /=)
Verilog/C (&, |, ^, ~, <<, >>, ==, !=)

VHDL 2008   std_logic ports async reset

Error report: mark english

Sim period: ns   save VCD   Board

(c) A. Trost, Fakulteta za elektrotehniko, LNIV, 2018

Ports & Signals   Add / Del

Circuit name
New

Name Modein,out, Typeu1,u2,u8,s2...



 
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