Default data type: bits
Operators:
VHDL (and, or, xor, not, &, =, /=)
Verilog/C (&, |, ^, ~, <<, >>, ==, !=)
VHDL 2008 std_logic ports async reset
Error report: mark english
Sim period: ns save VCD Board
(c) A. Trost, Fakulteta za elektrotehniko, LNIV, 2018