`timescale 1ns/1ps

module tb_avgN;
  logic clk = 0;
  logic in_valid = 0;
  logic signed [13:0] x = 0;
  logic signed [13:0] y;
  logic out_valid;

  avgN #(.N(4)) dut (
    .clk       (clk),
    .in_valid  (in_valid),
    .x         (x),
    .y         (y),
    .out_valid (out_valid)
  );

  // perioda ure 10 ns
  initial begin
    #10;
    forever begin
      clk = 1;  #5;
      clk = 0;  #5;
    end
  end

  // nastavi data in valid
  task automatic drive(    
    input logic signed [13:0] data,
    input logic valid
  );
    @(posedge clk);
    #1;
    x        = data;
    in_valid = valid;    
  endtask


initial begin
  in_valid = 0;
  x  = 0;

  // cikli 1-8: x=0
  repeat (4) begin
    drive(0, 1);
    drive(0, 0);
    drive(0, 0);
  end

  // impulz, x=80
  drive(14'd80, 1);
  drive(0, 0);
  drive(0, 0);
  
  // x=0
  repeat (6) begin
    drive(0, 1);
    drive(0, 0);
    drive(0, 0);
  end

  #10;
  $finish;
end

endmodule