library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE std.textio.all; use IEEE.NUMERIC_STD.ALL; entity grafikaTB is end grafikaTB; architecture Behavioral of grafikaTB is component grafika is port ( clk : in std_logic; n: in unsigned(3 downto 0); x,y: in unsigned(11 downto 0); rgb: out unsigned(5 downto 0) ); end component; signal clk: std_logic; signal n: unsigned(3 downto 0); signal x,y: unsigned(11 downto 0) := (others=>'0'); signal rgb: unsigned(5 downto 0); signal endsim: boolean := false; constant clk_period : time := 10 ns; begin uut: grafika port map (clk, n, x, y, rgb); clkp :process begin if not endsim then clk <= '1'; wait for clk_period/2; clk <= '0'; wait for clk_period/2; else wait; end if; end process; izhod: process file slika: text open write_mode is "slika.txt"; variable str: line; variable c: character; variable cnt: unsigned(5 downto 0):="000000"; begin wait until rising_edge(clk); c := '+'; if rgb="000000" then c := '-'; end if; if rgb="111111" then c := '*'; end if; write(str, c, right, 1); if x<100 then x <= x + 1; else x <= (others=>'0'); writeline(slika, str); if y<400 then y <= y + 1; else y <= (others=>'0'); endsim <= true; wait; end if; end if; end process; end Behavioral;