library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; use IEEE.math_real.all; entity TestSkala is end TestSkala; architecture Behavioral of TestSkala is component skala Port ( data : in signed (13 downto 0); dout : out signed (8 downto 0); clk : in STD_LOGIC; sely : in STD_LOGIC_VECTOR (1 downto 0)); end component; signal clk : std_logic:= '0'; signal data : signed(13 downto 0); signal sely: std_logic_vector(1 downto 0); signal dout : signed(8 downto 0); constant Ts : time := 30 ns; signal endsim: std_logic; begin uut: skala port map ( clk => clk, data => data, sely => sely, dout => dout ); -- Clock generator clk_gen: process begin if endsim='1' then wait; else clk <= '1'; wait for Ts/2; clk <= '0'; wait for Ts/2; end if; end process; -- Generiraj prelet sinusnega signala za vhod vezja in shrani izhod singen : process variable fi: real:= 0.0; variable si: integer; variable i: integer := 0; begin endsim <= '0'; sely <= "00"; for j in 0 to 20000 loop wait for Ts; fi := fi + 0.001; -- 0.001 = 1000 ciklov / periodo si := integer(1000.0*sin(MATH_2_PI*fi)+0.49); -- sinus, amp=100 data <= to_signed(si, 14); if j = 5000 then sely <= "01"; elsif j = 10000 then sely <= "10"; elsif j = 15000 then sely <= "11"; end if; end loop; endsim <= '1'; wait; end process; end Behavioral;