---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 05/11/2015 04:32:05 PM -- Design Name: -- Module Name: TB_VGAtest - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE std.textio.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity TB_VGAtest is end TB_VGAtest; architecture Behavioral of TB_VGAtest is component VGAtest is Port ( clk : in STD_LOGIC; hsync, vsync : out STD_LOGIC; rgb_o : out STD_LOGIC_VECTOR (7 downto 0)); end component; signal clk: std_logic; signal hsync,vsync: std_logic; signal rgb:STD_LOGIC_VECTOR (7 downto 0); signal clk50, en: std_logic := '0'; constant clk_period : time := 10 ns; begin u1: VGAtest port map (clk, hsync, vsync, rgb); clkp :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; clk50p: process(clk) begin if rising_edge(clk) then clk50 <= not clk50; end if; end process; izhod: process(clk50) file slika: text open write_mode is "slika.txt"; variable str: line; variable c: character; variable cnt: unsigned(5 downto 0):="000000"; begin if rising_edge(clk50) then if en='1' then c := '+'; if rgb="00000000" then c := '-'; end if; if rgb="11111111" then c := '*'; end if; write(str, c, right, 1); cnt := cnt + 1; if cnt=0 then writeline(slika, str); end if; else en <= '1'; end if; end if; end process; end Behavioral;