library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; use IEEE.math_real.all; entity TB_IPosc is end TB_IPosc; architecture Behavioral of TB_IPosc is component IPosc Port (clk : in STD_LOGIC; s1 : in STD_LOGIC; data : in signed (13 downto 0); selx : in STD_LOGIC_VECTOR (1 downto 0); sely : in STD_LOGIC_VECTOR (1 downto 0); adr : in unsigned (9 downto 0); dataout : out signed (8 downto 0) ); end component; signal clk : std_logic:= '0'; signal adr : unsigned(9 downto 0) := (others=>'0'); signal selx, sely: std_logic_vector(1 downto 0) := "00"; signal data : signed(13 downto 0); signal dataout : signed(8 downto 0); signal s1: std_logic := '0'; constant Ts : time := 30 ns; signal endsim: std_logic; begin uut: IPosc port map ( clk => clk, s1 => s1, data => data, selx => selx, sely => sely, adr => adr, dataout => dataout ); -- Clock generator clk_gen: process begin if endsim='1' then wait; else clk <= '1'; wait for Ts/2; clk <= '0'; wait for Ts/2; end if; end process; selx <= "01"; -- Generiraj prelet sinusnega signala za vhod vezja singen : process variable fi: real:= 0.0; variable si: integer; variable i: integer := 0; begin endsim <= '0'; for j in 0 to 20000 loop wait for Ts; fi := fi + 0.001; -- 0.001 = 1000 ciklov / periodo si := integer(1000.0*sin(MATH_2_PI*fi)+0.49); -- sinus, amp=100 data <= to_signed(si, 14); if j = 2000 then s1 <= '1'; elsif j = 2010 then s1 <= '0'; end if; end loop; for j in 0 to 750 loop adr <= to_unsigned(j, 10); wait for Ts; end loop; endsim <= '1'; wait; end process; end Behavioral;