---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 05/11/2015 04:32:05 PM -- Design Name: -- Module Name: TB_VGAtest - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE std.textio.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity TB_IPgraf is end TB_IPgraf; architecture Behavioral of TB_IPgraf is component IPgraf is Port ( clk50 : in STD_LOGIC; selx : in STD_LOGIC_VECTOR (1 downto 0); sely : in STD_LOGIC_VECTOR (1 downto 0); data : in UNSIGNED (8 downto 0); rgb : out STD_LOGIC_VECTOR (2 downto 0); hsync : out STD_LOGIC; vsync : out STD_LOGIC; cx0 : out UNSIGNED (9 downto 0)); end component; component graf is Port ( clk : in STD_LOGIC; cx : in unsigned (9 downto 0); data : out unsigned (8 downto 0) ); end component; signal clk: std_logic; signal hsync,vsync: std_logic; signal data: unsigned (8 downto 0) := (others=>'0'); signal selx,sely: STD_LOGIC_VECTOR (1 downto 0) := "00"; signal cx0: unsigned (9 downto 0); signal rgb:STD_LOGIC_VECTOR (2 downto 0); signal clk50, en: std_logic := '0'; constant clk_period : time := 10 ns; begin u1: IPgraf port map (clk50=>clk50, selx=>selx, sely=>sely, data=>data, rgb=>rgb, hsync=>hsync, vsync=>vsync, cx0=>cx0); u2: graf port map (clk=>clk50, cx => cx0, data => data); clkp :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; clk50p: process(clk) begin if rising_edge(clk) then clk50 <= not clk50; end if; end process; izhod: process(clk50) file slika: text open write_mode is "slika.txt"; variable str: line; variable c: character; variable cnt: unsigned(7 downto 0):="00000000"; begin if rising_edge(clk50) then if en='1' then c := '+'; case rgb is when "001" => c:='1'; when "010" => c:='2'; when "011" => c:='3'; when "100" => c:='4'; when "101" => c:='5'; when "110" => c:='6'; when "111" => c:='7'; when others => c:='0'; end case; write(str, c, right, 1); cnt := cnt + 1; if cnt=0 then writeline(slika, str); end if; else en <= '1'; end if; end if; end process; end Behavioral;