-------------------------------------------------------------------------------- -- Company: FE -- Engineer: A. Trost -- -- Design Name: testAXI_VGA -- Project Name: DIVS2016, 4. vaja, testna struktura -- Target Device: ZedBoard -- Tool versions: Vivado 2015 -- Description: Testna struktura za vmesnik na vodilu AXI Lite -- vsebuje proceduri za pisanje 32-bitnih podatkov na vodilo in branje vodila -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values USE ieee.numeric_std.ALL; ENTITY testAXI_VGA IS END testAXI_VGA; ARCHITECTURE behavior OF testAXI_VGA IS -- Testirana komponenta kvadrav vsebuje signale vmesnika AXI Slave (s0_axi) COMPONENT AXI_VGA_v1_0 is generic ( C_S00_AXI_DATA_WIDTH : integer := 32; C_S00_AXI_ADDR_WIDTH : integer := 4 ); port ( din: in STD_LOGIC_VECTOR (31 downto 0); hsync : out STD_LOGIC; vsync : out STD_LOGIC; dout: out STD_LOGIC_VECTOR (31 downto 0); rgb : out STD_LOGIC_VECTOR (7 downto 0); -- Ports of Axi Slave Bus Interface S00_AXI s00_axi_aclk : in std_logic; s00_axi_aresetn : in std_logic; s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); s00_axi_awprot : in std_logic_vector(2 downto 0); s00_axi_awvalid : in std_logic; s00_axi_awready : out std_logic; s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0); s00_axi_wvalid : in std_logic; s00_axi_wready : out std_logic; s00_axi_bresp : out std_logic_vector(1 downto 0); s00_axi_bvalid : out std_logic; s00_axi_bready : in std_logic; s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); s00_axi_arprot : in std_logic_vector(2 downto 0); s00_axi_arvalid : in std_logic; s00_axi_arready : out std_logic; s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); s00_axi_rresp : out std_logic_vector(1 downto 0); s00_axi_rvalid : out std_logic; s00_axi_rready : in std_logic ); end component AXI_VGA_v1_0; --Vhodi signal din : std_logic_vector(31 downto 0) := (others => '0'); signal S_AXI_ACLK : std_logic := '0'; signal S_AXI_ARESETN : std_logic := '0'; signal S_AXI_AWADDR : std_logic_vector(3 downto 0) := (others => '0'); signal S_AXI_AWPROT : std_logic_vector(2 downto 0) := "000"; signal S_AXI_AWVALID : std_logic := '0'; signal S_AXI_WDATA : std_logic_vector(31 downto 0) := (others => '0'); signal S_AXI_WVALID : std_logic := '0'; signal S_AXI_WSTRB : std_logic_vector(3 downto 0) := (others => '0'); signal S_AXI_BREADY : std_logic := '0'; signal S_AXI_ARADDR : std_logic_vector(3 downto 0) := (others => '0'); signal S_AXI_ARPROT : std_logic_vector(2 downto 0) := "000"; signal S_AXI_ARVALID : std_logic := '0'; signal S_AXI_RREADY : std_logic := '0'; --Izhodi signal dout : std_logic_vector(31 downto 0); signal hsync, vsync: std_logic; signal rgb : std_logic_vector(7 downto 0); signal S_AXI_AWREADY : std_logic; signal S_AXI_WREADY : std_logic; signal S_AXI_BVALID : std_logic; signal S_AXI_BRESP : std_logic_vector(1 downto 0); signal S_AXI_ARREADY : std_logic; signal S_AXI_RDATA : std_logic_vector(31 downto 0); signal S_AXI_RVALID : std_logic; signal S_AXI_RRESP : std_logic_vector(1 downto 0); -- Perioda ure constant S_AXI_ACLK_period : time := 10 ns; -- Kntrola simulacije signal sim : std_logic := '1'; BEGIN -- Unit Under Test uut: AXI_VGA_v1_0 PORT MAP ( din => din, dout => dout, hsync => hsync, vsync => vsync, rgb => rgb, s00_axi_aclk => S_AXI_ACLK, s00_axi_aresetn => S_AXI_ARESETN, s00_axi_awaddr => S_AXI_AWADDR, s00_axi_awprot => S_AXI_AWPROT, s00_axi_awvalid => S_AXI_AWVALID, s00_axi_awready => S_AXI_AWREADY, s00_axi_wdata => S_AXI_WDATA, s00_axi_wvalid => S_AXI_WVALID, s00_axi_wready => S_AXI_WREADY, s00_axi_wstrb => S_AXI_WSTRB, s00_axi_bvalid => S_AXI_BVALID, s00_axi_bready => S_AXI_BREADY, s00_axi_bresp => S_AXI_BRESP, s00_axi_araddr => S_AXI_ARADDR, s00_axi_arprot => S_AXI_ARPROT, s00_axi_arvalid => S_AXI_ARVALID, s00_axi_arready => S_AXI_ARREADY, s00_axi_rdata => S_AXI_RDATA, s00_axi_rvalid => S_AXI_RVALID, s00_axi_rready => S_AXI_RREADY, s00_axi_rresp => S_AXI_RRESP ); -- Proces za urni takt S_AXI_ACLK_process :process begin if sim='1' then S_AXI_ACLK <= '0'; wait for S_AXI_ACLK_period/2; S_AXI_ACLK <= '1'; wait for S_AXI_ACLK_period/2; else wait; end if; end process; -- Stimulatorji za testiranje komponente stim_proc: process -- write32, sekvenca za pisanje na vodilo procedure write32(adr: integer; data: integer) is begin wait until rising_edge(S_AXI_ACLK); S_AXI_AWADDR <= std_logic_vector(to_unsigned(adr, 4)); -- nastavi naslov in podatek S_AXI_WDATA <= std_logic_vector(to_unsigned(data, 32)); S_AXI_WSTRB <= x"F"; -- 32 bitni zapis S_AXI_AWVALID <= '1'; -- aktiviraj kontrolne signale S_AXI_WVALID <= '1'; S_AXI_BREADY <= '1'; wait until falling_edge(S_AXI_WREADY); -- cakaj zakljucek vpisa S_AXI_AWADDR <= x"0"; -- pobrisi vodilo (ni potrebno) S_AXI_WDATA <= x"00000000"; S_AXI_AWVALID <= '0'; -- deaktiviraj kontrolne signale S_AXI_WVALID <= '0'; wait until falling_edge(S_AXI_BVALID); -- cakaj zakljucek potrditve S_AXI_BREADY <= '0'; -- deaktiviraj kanal Response end write32; -- read32, sekvenca za branje vodila procedure read32(adr: integer) is begin wait until rising_edge(S_AXI_ACLK); S_AXI_ARADDR <= std_logic_vector(to_unsigned(adr, 4)); -- nastavi naslov S_AXI_ARVALID <= '1'; -- aktiviraj kontrolne signale za branje S_AXI_RREADY <= '1'; wait until falling_edge(S_AXI_ARREADY); -- cakaj zakljucek branja S_AXI_ARADDR <= x"0"; -- pobrisi naslov (ni potrebno) S_AXI_ARVALID <= '0'; -- deaktiviraj kontrolne signale wait until falling_edge(S_AXI_RVALID); S_AXI_RREADY <= '0'; end read32; begin S_AXI_ARESETN <= '0'; -- aktiven reset wait for 20 ns; S_AXI_ARESETN <= '1'; -- deaktiviraj reset wait for 10 ns; -- vpis vrednosti v vhodne registre write32(0, 3); -- barva ozadja write32(4, 16#ff0055#); -- vpis točke (0,255) vrednost 55 wait for 45940*S_AXI_ACLK_period; -- čakaj na prvo točko znotraj okna sim <= '0'; wait; end process; din <= dout; END;