---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 04/15/2015 04:57:17 PM -- Design Name: -- Module Name: VmesnikTB - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity VmesnikTB is end VmesnikTB; architecture Behavioral of VmesnikTB is component vmesnik is Port ( sck, ldcp : in STD_LOGIC; sin : in STD_LOGIC; clk : in STD_LOGIC; oreg: in STD_LOGIC_VECTOR (7 downto 0); reg : out STD_LOGIC_VECTOR (7 downto 0); sout : out STD_LOGIC); end component; signal sck, ldcp, sin, clk: std_logic := '0'; signal reg: std_logic_vector(7 downto 0); signal oreg: std_logic_vector(7 downto 0); signal sout: std_logic; signal simend: std_logic := '0'; signal hst: unsigned(10 downto 0):=(others=>'0'); signal cik: unsigned(2 downto 0):=(others=>'0'); signal sck2: std_logic; signal sr, sr595, reg595: std_logic_vector(7 downto 0); begin uut: vmesnik port map (sck, ldcp, sin, clk, oreg, reg, sout); simend <= '0', '1' after 500 us; c: process begin if simend='0' then clk <= '0'; wait for 20 ns; clk <= '1'; wait for 20 ns; else wait; end if; end process; psync: Process(clk) begin if rising_edge(clk) then if hst < 1040 then hst<=hst+1; else hst<=(others=>'0'); cik <= cik + 1; end if; sck2 <= sck; end if; end process; sin <= sr(7); p165: process(sck2, ldcp) begin if ldcp <= '0' then sr <= "10110011"; elsif rising_edge(sck2) then sr <= sr(6 downto 0) & '0'; end if; end process; p595: process(sck2, ldcp) begin if rising_edge(sck2) then sr595 <= sr595(6 downto 0) & sout; end if; if rising_edge(ldcp) then reg595 <= sr595; end if; end process; sck <= '1' when hst>=856 and hst<976 else '0'; ldcp <= '0' when cik=0 and hst>=600 and hst<700 else '1'; oreg <= "11001010"; end Behavioral;