---------------------------------------------------------------------------------- -- Company: FE -- Engineer: AT -- -- Create Date: 29.03.2016 21:48:32 -- Design Name: test asinhronega serijskega sprejemnika -- Description: DES 2015 -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity testSpr is end testSpr; architecture Behavioral of testSpr is -- serijski sprejemnik component sprejem Port ( clk : in STD_LOGIC; rx : in STD_LOGIC; data : out STD_LOGIC_VECTOR (7 downto 0); done : out STD_LOGIC ); end component; signal clk : std_logic := '0'; -- sistemska ura signal rx : std_logic := '1'; -- serijski signal signal rxdata: std_logic_vector(7 downto 0); -- sprejet podatek signal done : std_logic; -- signalizacija sprejema -- serijski oddajnik signal cnt: unsigned(1 downto 0) := "00"; -- oddajni stevec signal sr: std_logic_vector(9 downto 0) := "1111111111"; -- oddajni pomikalni register signal bc: unsigned(3 downto 0); -- stevec oddanih bitov signal data: std_logic_vector(7 downto 0) := X"23"; -- oddani podatek signal en: std_logic := '0'; -- omogoci oddajo signal konec: std_logic := '0'; -- ustavi simulacijo signal CP: time := 2170 ns; -- 4*115200 Hz begin -- testni serijski oddajnik p: process(clk) begin if rising_edge(clk) then cnt <= cnt + 1; -- stevec za deljenje ure if cnt=0 then if en = '1' then -- zacni oddajo podatka sr <= '1' & data & '0'; bc <= "1010"; end if; if bc>0 then -- pomikaj, dokler je stevec bitov > 0 sr <= '1' & sr(9 downto 1); bc <= bc - 1; end if; end if; end if; end process; rx <= sr(0); -- testirana komponenta uut: sprejem port map (clk, rx, rxdata, done); -- stimulatorji clk_gen: process begin if konec='0' then clk <= '0'; wait for CP/2; clk <= '1'; wait for CP/2; else wait; end if; end process; stim: process begin en <= '1'; -- nastavi serijski oddajnik data <= "00100011"; wait for CP; en <= '0'; -- pocakaj vsaj 10 serijskih period (10*4 clk) wait for 40*CP; konec <= '1'; wait; end process; end Behavioral;