library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; entity TB_SisVmesnik is end TB_SisVmesnik; Architecture Behavioral of TB_SisVmesnik is Component SisVmesnik Port ( clk_i : in std_logic; rstn_i : in std_logic; wdata_i : in std_logic_vector(31 downto 0); adr_i : in std_logic_vector(31 downto 0); wen_i : in std_logic; ren_i : in std_logic; rdata_o : out std_logic_vector(31 downto 0); err_o : out std_logic; ack_o : out std_logic; clk50 : in std_logic; reg : in std_logic_vector(7 downto 0); oreg : out std_logic_vector(7 downto 0); logox : out std_logic_vector(9 downto 0); logoy : out std_logic_vector(9 downto 0)); end Component; signal clk_i : std_logic:= '0'; signal rstn_i : std_logic:= '1'; signal adr_i : std_logic_vector(31 downto 0) := X"00000000"; signal wdata_i : std_logic_vector(31 downto 0) := X"00000000"; signal wen_i : std_logic := '0'; signal ren_i : std_logic := '0'; signal rdata_o : std_logic_vector(31 downto 0); signal err_o : std_logic; signal ack_o : std_logic; signal clk50 : std_logic; signal reg : std_logic_vector(7 downto 0) := "00000011"; signal oreg : std_logic_vector(7 downto 0); signal logox : std_logic_vector(9 downto 0); signal logoy : std_logic_vector(9 downto 0); constant T : time := 10 ns; constant T1 : time := 20 ns; BEGIN uut: SisVmesnik port map ( clk_i => clk_i, rstn_i => rstn_i, adr_i => adr_i, wdata_i => wdata_i, wen_i => wen_i, ren_i => ren_i, rdata_o => rdata_o, err_o => err_o, ack_o => ack_o, clk50 => clk50, reg => reg, oreg => oreg, logox => logox, logoy => logoy); -- Clock process definitions clk_process: process begin clk_i <= '1'; wait for T/2; clk_i <= '0'; wait for T/2; end process; clk50_process: process begin clk50 <= '1'; wait for T1/2; clk50 <= '0'; wait for T1/2; end process; stim_proc: process begin wait for 0.5 ns; rstn_i <= '0'; wait for T; rstn_i <= '1'; wdata_i <= X"01020304"; adr_i <= X"40600004"; -- naslov 0x00004 wen_i <= '1'; wait for T; wen_i <= '0'; wait for 10*T; wait; end process; END;