Selected References

 

ŽEMVA, Andrej, BRGLEZ, Franc, KOZMINSKI, Krysztof, ZAJC, Baldomir. A functionality fault model: feasibility and applications. V: Proceedings of European Design and Test Conference, 1994, pp. 152-158.

 

ŽEMVA, Andrej, ZAJC, Baldomir, BRGLEZ, Franc. Permissible perturbations: a premise for multi-level logic optimization. Proceedings of European Conference on Circuit Theory and Design, 1997, pp. 1327-1331.

 

ŽEMVA, Andrej, BRGLEZ, Franc, ZAJC, Baldomir. Multi-level logic optimization based on wave synthesis of permissible mutation functions (WASP). Proc. of  International Workshop on Logic Synthesis, 1998, Vol. 2, pp. 484-498.

 

ŽEMVA, Andrej, TROST, Andrej, ZAJC, Baldomir. A rapid prototyping environment for teaching digital logic design. IEEE Transactions on Education, 1998, Vol. 41, No. 4, suppl. CD-ROM, pp. 1-10.

 

ŽEMVA, Andrej, TROST, Andrej, ZAJC, Baldomir, Educational programmable system for prototyping digital circuits. Int. J. Electr. Eng. Educ., 1998, Vol. 35, No. 3, pp. 236-244.

 

TROST, Andrej, ŽEMVA, Andrej, ZAJC, Baldomir, A reconfigurable system for prototyping implementation of image processing algorithms. Elektrotechnical. Journal, 1999, Vol. 66, No. 2, pp. 77-83.

 

TROST, Andrej, ŽEMVA, Andrej, VERDERBER, Matjaž, Prototyping hardware and software environment for teaching digital circuit design. Int. J. Electr. Eng. Educ., 2001, vol. 38, no. 4, pp. 368-378.

 

FINC, Matjaž, TROST, Andrej, ŽEMVA, Andrej. A configurable prototype platform for real time HW/SW video and image processing, 2003, Design&Elektronik, pp. 673-682.

 

VERDERBER, Matjaž, ŽEMVA, Andrej, LAMPRET, Damjan. HW/SW partitioned optimization and VLSI-FPGA implementation of the MPEG-2 video decoder, 2003, Proc. of Eurpean Design and Automation Conference, Designers' forum, pp. 238-243.

 

FINC, Matjaž, TROST, Andrej, ZAJC, Baldomir, ŽEMVA, Andrej, HW/SW co-design of real-time video applications using a custom configurable prototyping platform Electrotechnical Journal, 2003, Vol. 70, No. 5, pp. 247-253.

 

VERDERBER, Matjaž, ŽEMVA, Andrej, TROST, Andrej. HW/SW codesign of the MPEG-2 video decoder. IPDPS, International Parallel and Distributed Processing Symposium, April 22-26, 2003, pp. 1-7 (CD ROM).

 

VERDERBER, Matjaž, ŽEMVA, Andrej, HW/SW partitioned optimization and VLSI-FPGA implementation of the MPEG-2 video decoder. MIDEM Journal, 2003, Vol. 33, No. 2, pp. 86-91.

 

FINC, Matjaž, ŽEMVA, Andrej. Practical approach to HW/SW co-design of embedded softcore processor systems, Proceedings of Embedded World 2004 Conference, pp. 585-594.

 

DEDIČ, Jože, TROST, Andrej, ŽEMVA, Andrej, Seamless HW/SW co-design flow, MIDEM Journal, 2004, Vol. 34, No. 1, pp. 18-25.

 

FINC, Matjaž, ŽEMVA, Andrej, Profiling Softcore Processor Applications for Hardware/Software Partitioning, Journal of System Architectures, 2005, Vol. 51, pp. 315-329.

PLATIŠE, Uroš, CVIKL, Matej, ŽEMVA, Andrej. Efficient implementation of a three-channel ECG digital acquisition module, Inf. MIDEM, 2005, Vol. 35, pp. 20-27.

FINC, Matjaž, ŽEMVA, Andrej. A systematic approach to profiling for hardware/software partitioning. Comput. electr. eng., 2005, Vol. 31, pp. 93-111.

VAUPOTIČ, Marko, MUŠČET, Marinko, ŽEMVA, Andrej. Razvoj platforme za zagotavljanje množice telekomunikacijskih storitev v sistemih sinhrone digitalne hierarhije. Elektroteh. vestn., 2006, letn. 73, št. 4, str. 189-194.

BAŠA, Kristjan, ŽEMVA, Andrej. Lead-acid battery state-of-charge estimation for induction motor forklift trucks, Inf. MIDEM, 2006, Vol. 36, št. 1, str. 37-43.

ŽEMVA, Andrej, VERDERBER, Matjaž. FPGA Oriented HW/SW Implementation of the MPEG-4 Video Decoder, Microprocessors and Applications, 2007, in print.

CVIKL, Matej, JAGER, Franc, ŽEMVA, Andrej. Hardware Implementation of a Modified Delay-Coordinate Mapping-Based QRS Complex Detection Algorithm, Journal of Applied Signal Processing - Special Issue on Advances in Electrocardiogram Signal Processing and Analysis, 2007, in print.

 

ZUPANČIČ, Srečko, POLANŠEK, Gregor, ŽEMVA, Andrej. Optimum VoIP packet routing using a communications processor, AEÜ International Jornal of Electronics and Communications, 2007, in print.